Zoom In
Chip Design Hub to Heighten Japan’s AI Competency

dvanced Industrial Science and Technology (AIST) and The University of Tokyo have established AI Chip Design Hub at Takeda Building, Asano Section in Hongo Campus of The University of Tokyo, leveraging partnership to accelerate the development of innovative artificial intelligence (AI) chips in Japan.

AI Chip Design Hub will make use of “Subsidies to Realize Development of Industrial Technologies” (Project on constructing verification environment for accelerating the development of AI chips), which was jointly proposed by AIST and The University of Tokyo and adopted by the Ministry of Economy, Trade and Industry (METI), and “Project for Accelerating Innovative AI Chip Development of New Energy and Industrial Technology Development Organization (NEDO)”.

It will provide small- and medium-size companies and venture companies, which aim to develop AI chips, with an AI chip design environment, consisting of electronic design automation (EDA) tool and emulator; common foundation, such as design flow and reference designs; design assets and know-how accumulated at the hub; and an environment to nurture human resources who design AI chips. Through these activities, the hub aims to contribute to the acceleration of AI chip development of small- and medium-size companies and venture companies in Japan, and at the same time, accelerate the development of AI chips through industry-government-academia cooperation.

Outline of AI Chip Design Hub
Fig. 1: Outline of AI Chip Design Hub
One-Stop Design Source
AI Chip Design Hub installs leading-edge electronic design automation (EDA) tools and large-scale logic verification equipment using the METI project and the NEDO project. It puts in place an AI chip design and verification environment, and at the same time, it provides a design flow, which includes an emulator, and tool chains. Furthermore, the hub will also develop design foundations, including reference designs for companies with no experience on AI chip development; sensor device models with sensor function for AI chip development; and libraries indispensable for prototyping AI chips at semiconductor manufacturing bases in Japan, and will be made available to qualified AI chip developers. In parallel with these activities, it will also nurture human resources with the aim of enhancing the level of human resources engaged in the development of integrated circuits.

Aside from EDA tools relating to the upstream design for designing AI chips’ functions and behaviors in the logic circuit level, under the NEDO project, tools relating to physical design, including the creation of AI chip designs by appropriately arranging and wiring libraries based on the results of upstream design, and the inspection of designs, will be installed at the hub. Furthermore, it will also put in place an environment for using an emulator that can verify 10 billion cycles of a large-scale AI chip circuit with 2.3 billion gates in several hours.

In addition, the hub will be designed for use on-site or at remote locations, ensuring high secrecy of users. It will support small- and medium-size and venture companies with various AI chip design environments. If users own a relatively high-performance computer, they can install an EDA tool in their computers and use them following license authentication. If users do not have a high-performance computer, they can use tools on the private cloud installed at the hub.

Furthermore, local small- and medium-size and venture companies can use EDA and other tools at the booths installed on local satellite hubs. In the Kyushu region, Fukuoka Industry, Science & Technology Foundation (Fukuoka IST) has established a local satellite hub in Robot system Development Center (Fukuoka Institute of System LSI Design Industry).