Industry Insight
Foundry Giants Race for Leadership in Chip Packaging Technology

s scaling down of chip sizes is facing its limit at 10nm node and below, the next logical step is to channel innovations in the chip packaging technologies, particularly in wafer level packaging (WLP).

The rapid emergence of heterogeneous computing architecture has also been driving innovations in the chip packaging technologies, giving birth to system in package (SiP) technology that allows chip makers to pack multiple dies into a single-package solution.

The chip making industry’s rapid ramp up to these advanced chip packaging technologies aims to keep up with the industry’s growing aspiration to embed more functionalities in the chip- or package-level without compromising power consumption and form factors. That aspiration, in turn, aims to keep up with the growing convergence of computing and communications, software, artificial intelligence (AI) algorithm, and even vision and speech sensing technologies on a system level, as makers try to put everything into their devices to make them as intelligent as humans.

Latest Chip Packaging Techniques
There are many kinds of advanced chip packaging technologies: 2D/3D through silicon via (TSV) packaging, embedded multi-die interconnect bridge (EMIB), wafer-level packaging, and SiP.

Wafer-level packaging technologies pack chip dies on a wafer and then dice them out of the wafer, and are classified into fan-in chip scale package (CSP) and fan out.

CSP is a fan-in technology, wherein single input and output lines are located on solder balls. It is more suitable for ultrasmall form factor devices, like wearables. However, heat dissipation is a big challenge. Meanwhile, fan-out technology fans out interconnects, reserving spaces for more input-outputs (I/Os), making it a better option to take the heat out of packages.

In 2D/3D packaging technologies, different dies are stacked on top of each other and TSV run through separated interposer dies from bottom to top. The technology is mainly used to pack different dies, like memory chip and CPUs, guaranteeing high bandwidth, but is too expensive to be used in low- and middle-end applications.

As system makers are now trying to put more of functions in small form factors, so are chipmakers. As a result, traditional chip packaging companies and chipmakers alike are turning to these advanced chip packaging technologies for the future.

Especially when it comes to foundry chip makers, embracing these advanced chip packaging technologies has become a key to competition. A case in point is the race between the largest foundry chipmaker Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) and Samsung Electronics Co., Ltd.’s foundry business unit for the leadership in the chip packaging technology.

Apple Opts for TSMC’s InFO Packaging Technology
Back in 2016, TSMC had outbid Samsung’s foundry business units to supply wafer for Apple Inc. and supplied its high-density fan out chip packaging technology for Apple’s applications processor chips for iPhone 7.

TSMC’s fan out chip packaging technology called integrated fan-out (InFO) is an InFO package-on-package (PoP) 3D stacking technology that stacks memory dies on application processor dies on a motherboard.

In 2015, TSMC InFO integrated 16nm SoC and DRAM chip in an advanced mobile application, and from there, started volume production in the first half of 2016. Since then, the technology has evolved rapidly to keep up with demand from Apple.

TSMC’s InFO is considered a packaging technology of choice, as it outperforms others in form factor, radiation protection, costs, and performance. It is particularly suitable for the integration of wireless systems that require lower power consumption, good heat dissipation, and high bandwidths, which are ideal features for smartphones, devices for internet of things (IoTs), and tablet PCs.

The latest of TSMC’s InFO technology is employed in Apple A11 application processor, using copper pillars called through info vias (TiVs) to replace through mold via (TMV) through a modeled via.

Available FOWLP process flows in high-volume manufacturing
Available FOWLP process flows in high-volume manufacturing
Samsung Focuses on RDL
In an effort to regain the foundry outsourcing contract from Apple, Samsung’s foundry business unit has been focusing on the legendary redistribution layer (RDL) interposer and fan-out system-in-package (FoSiP) technologies.

The RDL interposer packaging technology is among the 2.5D chip packaging technologies that are widely used to pack together different kinds of chips on a packaging substrate, squeezing interposers in between chip dies and substrates. The RDL technology comes out of nowhere, but was originally developed out of the necessity to address flip chip packaging technology’s challenges – the lack of area array.

RDL was originally considered as a stopgap technology, but today has made a niche in advanced packaging technology.

RDL is an organic thin film that interconnects electric-conductive wires and is deposited on the interposer to interconnect different kinds of chips, like DRAMs and CPUs. It is an underlying technology that is instrumental in developing today’s advanced packaging technologies, like fan-in and fan-out WLP, and TSV applications, such as CMOS image sensor packaging, silicon interposers for 3D integration, and 3D integration with backside TSV. As the RDL interposer technology costs less than TSV, it is rapidly emerging as a cheaper alternative to prohibitively expensive silicon interposer.

Depositing RDL is relatively simple; the first thing to do is to deposit RDL on a carrier, and then place and bond chip dies on RDL. The next step is to encapsulate all dies and carriers. Then, the carrier is detached from RDL to grind and attach balls. To finish the packaging processes, the RDL interposer has to be molded to the substrate.

The RDL interposer chip packaging technology is a good fit for low-cost application processors and high-performance computing (HPC) SoC, which calls for as many I/Os as possible regardless of the form factor.

Samsung had already released a mechanical sample RDL interposer chip package in the Q4 of 2018. It packs together four high bandwidth memory chips and one logic chip on the RDL interposer.

By 2025, Samsung plans to start commercial production of RDL interposer chip packaging solutions in high volume.

The RDL technology is an underlying chip packaging technology, around which almost all of Samsung’s advanced chip packaging technologies will be built. For example, Samsung is working on FoSiP packaging chip technologies, with memory chips and application processor packed together next to each other in parallel using the RDL interposer technology. With this FoSiP technology on hand, Samsung plans to pack one application processor and six DRAM chips on a single package substrate, placing a set of six stacked DRAM chips and the application processor next to each other. Six DRAM chips are to be stacked one after another through silicon via hole. Then, the stacked set of six DRAM chips are placed next to an application processor on the RDL interposer.

The parallel layout offers better heat dissipation than fan-out package-on-package (FoPoP) technology, but has a bigger package size. For example, FoSiP technology boasts of 24 percent better heat dissipation than FoPoP technology.