In Focus
In Focus
Advanced System-in-Package Solution Drives Heterogeneous Integration
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s IBM Chief Executive Officer Arvind Krishana puts it, the novel coronavirus disease (COVID-19) pandemic will dramatically accelerate adoption of artificial intelligence (AI) and cloud computing, as more people maximize the potentials of online platforms from shopping, to meeting, learning, and even on movie and live video streaming service sites for work, learning, and even leisure.

Adding to that metrics, the rapid penetration of 5G communications services and smart manufacturing are also clamoring for more compute power, more storage spaces, wider data transmission bandwidth, and other low data latency input-output (I/O) solutions to keep up with the rising demand in data traffic.

These strong system requirements are calling for chip makers to innovate on their chip making technologies, including chip design, processing and even packaging solutions, as they face a daunting task to pack all different functional silicon elements together on a single die or a circuit board in heterogeneous integration or computing.

As costs of chip node scaling goes through the roof, however, chip makers are looking to advanced chip packaging technologies to tackle those challenges.

True enough, there already have been many different heterogeneous integration options on a multiple of system in package (SiP) solutions. Since 2012, field programmable gate array (FPGA) maker Xilinx, Inc. has shipped many of its FPGA solutions with high bandwidth memory stacks on heterogeneous integration package solution called silicon interposer.

Advanced System-in-Package Solution Drives Heterogeneous Integration
A

s IBM Chief Executive Officer Arvind Krishana puts it, the novel coronavirus disease (COVID-19) pandemic will dramatically accelerate adoption of artificial intelligence (AI) and cloud computing, as more people maximize the potentials of online platforms from shopping, to meeting, learning, and even on movie and live video streaming service sites for work, learning, and even leisure.

Adding to that metrics, the rapid penetration of 5G communications services and smart manufacturing are also clamoring for more compute power, more storage spaces, wider data transmission bandwidth, and other low data latency input-output (I/O) solutions to keep up with the rising demand in data traffic.

These strong system requirements are calling for chip makers to innovate on their chip making technologies, including chip design, processing and even packaging solutions, as they face a daunting task to pack all different functional silicon elements together on a single die or a circuit board in heterogeneous integration or computing.

As costs of chip node scaling goes through the roof, however, chip makers are looking to advanced chip packaging technologies to tackle those challenges.

True enough, there already have been many different heterogeneous integration options on a multiple of system in package (SiP) solutions. Since 2012, field programmable gate array (FPGA) maker Xilinx, Inc. has shipped many of its FPGA solutions with high bandwidth memory stacks on heterogeneous integration package solution called silicon interposer.

chart of co-packaging solutions of photonics engine and electronic ICs
Companies have started working on next generation of co-packaging solutions of photonics engine and electronic ICs.
From 2015, CPU chip maker Advanced Micro Devices, Inc. (AMD) has also shipped a silicon interposer-based heterogeneous integration packaging solution that stacks together graphical processing unit (GPU) and high bandwidth memory on a package substrate. The AMD Radeon RX Vega 10 GPU is an heterogeneous integration solution that comes built with 14nm FinFET GPU and 8GB HBM2 on a substrate using a 27×29mm silicon interposer. The silicon interposer is an electrical interface routing technology that connects one socket to another to send back and forth data between silicon elements like memory and GPU or CPU.

Heterogeneous Integration on SiP
GPU chip maker NVIDIA Corporation has multiple versions of silicon interposer-based advanced chip packing solutions. One of them is NVIDIA’s GPU solution with four high bandwidth memories mounted on a silicon interposer that measures 34×43mm.

NVIDIA’s latest A100 GPU also uses a silicon interposer technology to string together a GPU and six high bandwidth memories on a substrate. NVIDIA is also tapping the possibility of using a new breed of chip packaging technologies called as Fan-out on Substrate (FOCoS). FOCoS is a sort of wafer-level packaging that dice chip dies on a silicon wafer, then position them on a thin reconstituted or carrier wafer and mold them with redistributed layer, and finally form solder balls atop them.

Taiwanese chip packaging company ASE Group is one of the chip packaging companies that work on the FOCos technology. The company displayed a couple of FOCos solutions at the Heterogeneous Integration Innovation Zone of SEMICON Taiwan.

“We can cram a range of ASICs from two up to eight or more than 10 on our FOCos solutions using different processor node technologies. That will be the trend. ASE’s FOCos solutions are offering FOCos solutions for high performance computing,” said Teck Lee, Senior Manager with Corp. R&D ASE.

TSMC works on integrated fan-out on substrate (InFO-oS) using RDL with 2µm line and space. The Taiwanese foundry chip maker has a rich portfolio of advanced chip packaging solutions as the company believes that the technology is very instrumental in heterogeneous computing system.

The Taiwanese foundry chip maker works on InFO Local Silicon Interconnect (LSI) + redistributed layer Interconnect (InFO-L) for ultra-high bandwidth chiplet integration that integrates SoC chips with high density bridge-like local silicon (Si) interconnect. The technology will be qualified in the first quarter of 2021, and will be mainly used with heterogeneous SoC solutions of CPU and HBM.

Another variation of TSMC’s InFO packages solutions is InFO system on integrated substrate (SoIS), a high-density heterogeneous package using an organic redistributed layer interposer with up to six interconnections layers. The organic redistributed layer uses copper (Cu) traces in low-k dielectric rather than Cu traces in SiO2 used for Si interposer.

The solution provides good electrical performances featuring low jitters, no layer-to-layer crosstalk, lower insertion loss. The solution comes as a cost competitive alternative to large, high-density substrates where yield and power consumption are challenges.

Leads in Innovations
Amkor Technology, Inc. has introduced silicon wafer integrated fan-out technology (SWIFT), which will come online next year.

man testing chip packaging technology
Fan-out on Substrate (FOCoS), an emerging new breed of chip packaging technology, takes center stage at SEMICON Taiwan.
Intel has lined up embedded multi-die interconnect bridge (EMIB) that uses silicon bridges for chip-to-chip communication with no through silicon via (TSV). Intel’s EMIB allows the die I/O or bumps to be placed as close as possible to the edge of the die because fewer I/O or bumps are required, providing a high-density localized interconnect between FPGA and transceiver dies.

IBM has its own direct bonded heterogeneous integration (DBHi) Si bridge packaging solution.

Siliconware Precision Industries (SPIL) of Taiwan has qualified a fan-out embedded bridge (Fo-EB) RDL test solution with 10µm line and space using microbumps to connect each dies to redistributed layer. The solution is mainly used with heterogeneous integration solutions of CPU and high bandwidth memory, GPU, and network router.

Chip packaging innovations do not stop there. Some companies are already working on a next generation of co-packaging solutions of photonics engine and electronic ICs, trying to combine optical interfaces with silicon dies for costs, power, and performance advantages. For example, companies like HPE are trying to create an ecosystem for this solution to make them deliverable.

Intel has demonstrated co-packaged optics Ethernet switch that integrates 1.6Tbps silicon photonics engine with 12.8Tbps programmable Ethernet switch.

The co-packages modules are designed for 25.6Tbps and 51.2Tbps switch generations for hyperscale datacenters.

Looking forward to the next 10 to 20 years, the industry will also bet on the emerging chiplet packaging solution. It will emerge as a de facto standard, as there are many drivers for the adoption, including strong demand for cost-effective solutions and desire to reuse IP. AMD is working on the technology on organic substrate.

TSMC is introducing SoIC that stacks chips together without bump-bonding processes in what’s called as hybrid bond or direct connect bond.

On top of cost and electrical performance advantages, these solutions will also offer cuts in power consumption and faster time to market.

10 to 20 Years Ahead
Intel’s Foveros chip packaging solution is gaining big attentions, as the solution allows dies stacked on an active interposer, which comes built together with power management features, voltage regulators, and DC/DC converters. Its benefits are plentiful, including reduced voltage drops, power efficiency, fast power delivery to CPU cores, and system-wide communication across multiple chiplets. It can allow system vendors to eliminate passive components on substrate.

As first application, the technology was in with Samsung’s Galaxy Note S mobile PC, offering longer battery life, fanless, and thin form factor. The solution comes built with Intel’s Lakefield CPU on a 22nm Active Si interposer.