Synopsys, Inc. has announced Samsung Electronics’ first successful production tapeout for its high-performance mobile SoC design, including flagship CPUs and GPUs. Specifically, with 300MHz higher performance using Synopsys.ai™ full stack AI-driven EDA suite and Synopsys IP on Samsung Foundry’s latest Gate-All-Around (GAA) process technologies.

With Generative AI

This achievement underscores the collaboration between Synopsys and Samsung to deliver exceptional performance, power, and area (PPA) for mutual customers. Thus, enabling a new chips with generative artificial intelligence (AI) capabilities on Samsung Foundry advanced process nodes.

“Our longstanding collaboration has delivered leading-edge SoC designs. This is a remarkable milestone to successfully achieve the highest performance, power, and area. Particularly, on the most advanced mobile CPU cores and SoC designs in collaboration with Synopsys,” said Kijoon Hong, vice president of SLSI at Samsung Electronics.

In addition, Hong said the partnership has established an ultra-high-productivity design system that delivers impressive results consistently. Moreover, it demonstrated how AI-driven solutions can help achieve PPA targets.

Meanwhile, Shankar Krishnamoorthy, General Manager of the EDA Group at Synopsys, also cited the importance of the partnership with Samsung. “The relentless demand for ever-better PPA and energy efficiency in high-performance mobile chips is driving the need for high-performance core-specific EDA optimization across the full stack,” said Krishnamoorthy.

“Our extensive set of PPA-boosting capabilities targeted for CPUs and GPUs across the Synopsys AI-driven EDA suite and IP portfolio. (Thus, enabling) our mutual customers to successfully design chips with the highest quality-of-results for the most advanced Samsung GAA processes.”

Yields Better Performance

Samsung used Synopsys’ Synopsys.ai EDA suite, utilizing Synopsys Fusion Compiler™ RTL-to-GDSII solution for superior PPA paired with Synopsys DSO.ai™. This further optimized design targets and maximized quality of results. Thus, this resulted in stringent performance and low-power requirements for Samsung’s mobile SoC design.

In addition, the system Samsung also utilized the high-performance core-specific techniques. This includes design partitioning optimization, multi-source clock tree synthesis (MSCTS), advanced wire optimization to minimize crosstalk, and virtual-flat hierarchical solution in the Synopsys Fusion Compiler solution.

As a result, Samsung was able to achieve 300MHz higher performance than alternative approaches. At the same time, it also achieved 10% lower dynamic power, all while saving Samsung weeks of manual design effort.

3 May 2024