Intel Foundry Services (IFS) and Cadence Design Systems Inc. have sealed a multiyear strategic agreement. Specifically, they will jointly develop a portfolio of key customized intellectual property (IP), optimized design flows, and techniques for Intel 18A process technology. It will focus on RibbonFET gate-all-around transistors and PowerVia backside power delivery.

Joint customers of the companies will be able to accelerate system-on-chip (SoC) project schedules on process nodes from Intel 18A and beyond. At the same time, optimizing for performance, power, area, bandwidth, and latency. Particularly, for demanding artificial intelligence, high performance computing, and premium mobile applications. 

Advances Intel’s IDM2.0

Stuart Pann, Intel senior vice president and general manager of IFS, said, “We will leverage Cadence’s world-class portfolio of leading IP and advanced design solutions to enable our customers to deliver high-volume, high-performance, and power-efficient SoCs on Intel’s leading-edge process technologies.”

Meanwhile, Anirudh Devgan, president and chief executive officer at Cadence, said, “We furthered our partnership with Intel Foundry Services through a significant strategic multiyear agreement to provide design software and leading IP at multiple Intel advanced nodes. Thereby, advancing Intel’s IDM 2.0 strategy and accelerating mutual customer success.”

Fast-growing market segments – such as artificial intelligence/machine learning, HPC and premium mobile computing – require the latest standards in IP. This way, it will be able to take advantage of advanced packaging and silicon process technologies.

Cadence’s leading-edge implementations of trailblazing standards, such as advanced memory protocols, PCI Express, UCI Express, and others for these key segments. Moreover, enable joint customers to achieve scalable, high-performance designs that accelerate their time to market in IFS’ most advanced silicon technologies and 3D-IC packaging capabilities.