Siemens Digital Industries Software has introduced Tessent Hi-Res Chain software. Accordingly, the new tool can address the critical challenges faced by integrated circuit (IC) design and manufacturing teams in advanced technology nodes. Specifically, even minor process variations can significantly impact yield and time-to-market. 

As IC designs progress to more advanced nodes at 5nm and below, they become increasingly susceptible to manufacturing variations. This can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate.

For that reason, Siemens has introduced Tessent Hi-Res Chain tool to address this problem. Particularly, it rapidly provides transistor-level isolation for scan chain defects.

Accelerates Yield Ramp

For advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles. 

Ankur Gupta, vice president and general manager of the Digital Design Creation Platform division, said the new tool is a major leap forward. “Tessent Hi-Res Chain represents a major leap forward in our ability to rapidly identify and address yield-limiting factors in advanced IC designs.”

In addition, Gupta said, “By providing unprecedented accuracy and resolution in defect isolation, we’re empowering our customers to accelerate their yield ramp. (Also, it) improve(s) time-to-market for cutting-edge semiconductor products.” 

Best-in-Class Solution

By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), Tessent Hi-Res Chain transforms failing test cycles into actionable insights. Thus, the solution employs layout-aware and cell-aware technology. This pinpoints a defect’s most probable failure mechanism, logic location, and physical location. 

Moreover, Tessent Hi-Res Chain builds on Siemens’ market-leading chain diagnosis capabilities. Therefore, offering precise defect isolation, even for point defects deep within design control signal networks.  

The new solution maintains Tessent industry-leading accuracy rate, with over 80 percent of its generated reports consistently confirmed through FA processes using Tessent technology. This high level of reliability has made Tessent the go-to solution for yield ramping across multiple technology nodes. 

Tessent Hi-Res Chain is part of Siemens’ comprehensive Tessent product family. Particularly, it offers best-in-class solutions for IC test, functional monitoring, and silicon lifecycle management. These tools work in concert to provide the highest test coverage, accelerate yield ramp, and improve quality and reliability throughout the silicon lifecycle. 

In this link, Siemens has provided more information about Tessent Hi-Res Chain and its full suite of IC design and test solutions.  

Siemens Digital Industries helps organizations digitally transform using software, hardware, and services from the Siemens Xcelerator platform.

Moreover, Siemens’ software and the comprehensive digital twin enable companies to optimize their design, engineering and manufacturing processes. Specifically, to turn today’s ideas into the sustainable products of the future. From chips to entire systems, from product to process, across all industries. 

10 July 2024