Socionext is broadening its use of agentic artificial intelligence across chip development, extending AI-driven methodologies into the physical design of large-scale 3nm system-on-chip (SoC) devices through an expanded collaboration with Cadence.

The move represents the company’s latest step in applying AI beyond individual engineering tasks and into broader design workflows, as semiconductor developers seek new ways to manage rising design complexity, improve productivity, and preserve specialized engineering knowledge.

Socionext said it is already using agentic AI in front-end design activities to improve design and verification efficiency while supporting engineering analysis and decision-making. The company is now bringing similar AI-driven capabilities into physical design, an increasingly challenging stage of development for advanced-node devices.

AI Moves Deeper Into Semiconductor Design

Under the collaboration, Socionext is applying the Cadence InnoStack AI Super Agent to the physical design of a large-scale 3nm SoC. The company said it intends to expand the technology’s use across additional SoC development projects.

According to Socionext, the initiative combines AI agents with advanced electronic design automation tools and design flows to improve engineering productivity and design quality.

“Socionext has already incorporated AI into front-end design activities and is applying AI-driven design to the physical design of a large-scale 3nm SoC,” said Hisato Yoshida, president and COO of Socionext. “We expect to achieve up to 5X overall productivity gains through Cadence’s agentic AI workflow.”

Yoshida added that the company aims to combine its design methodologies and engineering experience with Cadence technology to help engineers focus on higher-value innovation across the development process.

Turning Engineering Expertise Into Reusable Assets

A central element of the effort involves embedding internal engineering knowledge directly into physical design workflows.

Socionext said it is using retrieval-augmented generation (RAG), Model Context Protocol support, custom AI skills, and AI agents to make accumulated expertise more accessible across projects and teams. Current and planned applications include floorplanning, timing-analysis checks, and checklist automation.

“As semiconductor design complexity grows, engineering organizations need better ways to capture and reuse expertise across projects and teams,” said Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence.

Teng said the implementation demonstrates how organizations can incorporate proprietary methodologies and engineering knowledge into AI-assisted design environments.

Toward an End-to-End AI-Driven Design Flow

Looking ahead, Socionext plans to connect its existing front-end AI initiatives with its growing AI-driven physical design capabilities to create a more integrated approach across the SoC development flow.

The company also plans to continue developing custom AI agents and engineering assistants designed to leverage internal expertise, improve productivity, and strengthen knowledge reuse across future chip development programs.

21 October 2026