Recent decades have shown mammoth technological advancements that paved the way to new trends, pushing to the limit the growth of computing needs. In fact, the number of devices per chip and systems performance has drastically increased. For that reason, the hunger for more performance and integration has speed up trends in logic scaling.

Sri Samavedam, Senior Vice President of CMOS Technologies at imec noted many applications that drive leading edge CMOS logic scaling. Indeed, the last decade alone has seen tremendous growth in compute needs for machine learning training.

“With the increasing complexity of training models with billions or more than trillion parameters, the compute needs are doubling every 3.5 months, much faster than Moore’s Law,” said Samavedam.

In the future, Samavedam said compute demand for machine learning will continue in the datacenter field. In addition, demand from applications like 5G infrastructure and autonomous driving vehicles will also become important drivers for advanced CMOS scaling.

imec has been an industry-wide hub for expertise, equipment, and materials for co-developments in the evolutions of new architectures and integration schemes. The organization leverages its advanced R&D in 300mm and 200mm pilot lines and a strong network of partners to drive innovation in advanced semiconductor scaling, silicon photonics, 3D system integration, and among many others.

In this interview with Asia Electronics Industry (AEI), Samavedam discusses the trends, challenges, and the future track in systems scaling that will make mark in the industry.

AEI: Can you enumerate the significant trends happening in logic CMOS scaling?

Samavedam: There is a transition from finFET devices to nanosheet gate-all-around devices happening at the 2 to 3nm nodes. These devices provide better gate control than tri-gate finFETs, which will allow some scaling of gate-length. Moreover, nanosheets also enable higher drive per footprint especially on scaled logic standard cells which only have single fin devices.

At the 2nm node, we will be entering the 4th generation of EUV patterning. Many pitches below 32nm will require multiple EUV exposures which impacts throughput and cost. A higher numerical aperture EUV tool (NA=0.55) might be introduced in the 2026 to 2027 timeframe. This will provide some relief in throughput with improved resolution.

Now, as the unit process steps are becoming more complex, it stretches the capabilities of existing tools. For that reason, there is a need for more high aspect ratio, deposition, etch and cleans both in the vertical and lateral dimensions.

In addition, there is also a need for new materials like different spacers that have good etch contrast relative to conventional oxides and nitrides. Due to the complexity of integration flows, the timeline between full nodes is increasing from ~2 years to ~2.5 years. More intermediate nodes are being introduced with incremental scaling and performance improvements.

Using the wafer backside for power delivery to the devices is the next major performance booster. Hence, there is a need to use conventional metal layers on the frontside of the wafer for routing signals while metal layers at the back of the wafer for power delivery. Separating the power delivery and signal routing enables lower voltage drop in the power supply, which improves performance. Furthermore, it reduces congestion of metal routing on the frontside. Intel has announced that they will introduce this at the 2nm node with nanosheet devices.

AEI: Which of these technologies you think will have significant impact on systems scaling and will make mark in the industry in the years to come?

Samavedam: Gate-all-around nanosheet devices are here to stay for a long time. Even when considering complementary FETs (CFETs) devices, stacking N and P devices in a compact footprint, we expect them to be built using nanosheets.

We expect to see System Technology Co-optimization (STCO) to play a key role in future systems scaling. Different functions of the traditional SoC will be partitioned, especially in high performance computing, to implement in different technologies nodes into chiplets. With SRAM scaling slowing down dramatically, it does not make sense to build large caches in the most advanced node. It may be more cost effective to build this in an older node and connect using 3D integration technology like die-to-wafer bonding.

The use of the wafer backside for power delivery opens other opportunities to create more functionality on the wafer backside. Active or passive devices like ESD diodes, MIMCAPs, power switches using deposited semiconductors, etc., could be built on the wafer backside to save area on the front-side and create new functions.

AEI: Can you name some of the challenges in logic scaling the industry is facing now?

Samavedam: Static RAM (SRAM) scaling has slowed down in the recent nodes. There used to be 50% area scaling of SRAMs (0.7 linear shrink) node to node. Due to slow-down in gate length scaling and contact poly pitch (CPP) scaling, SRAM scaling has slowed down dramatically.

There is also a drive to identify specific technologies to address system bottlenecks like the memory wall or the power wall instead of relying on off-the-shelf generic technologies. Thus, we refer to this as System Technology Co-optimization (STCO). For example, AMD’s V-cache technology, which uses 3D integration to bring extra SRAM memory closer to the CPU. In addition, the use of a silicon interposer bridge to connect two CPU die in the Apple M1 Ultra system-on-chip (SoC).

Besides SRAM scaling, standard cell scaling is also challenging. Particularly, having sufficient active device width (drive strength) in each footprint. Also, fitting the high k gate dielectric and the work-function setting metals between the nanosheets is another major challenge.

Companies that use advanced logic nodes in their products, face challenges with regards to EUV throughput and rising node to node costs.

Meanwhile, in the back end, RC scaling and via resistance pose a great challenge as metal pitches scaled below 20nm.

AEI: What steps imec are doing from its end to address these challenges?

Samavedam: To address the slowdown in SRAM and standard cell scaling, imec invented a device architecture called the forksheet, which scales the N to P space. Particularly, this allows for more active device width (more drive strength) in each footprint. The forksheet device also leverages much of the integration flow of nanosheets. Furthermore, there are some challenges tied to preserving the dielectric between N and P devices that still need to be addressed. The device architecture beyond nanosheets and forksheets is complementary FETs (CFETs), stacking N and P devices on top of each other using a complex integration.

On the other hand, in back-end metallization, copper dual-damascene integration will give way to high aspect ratio metal etch to pattern lines below 20nm pitch. We have been focusing on enabling ruthenium for direct metal etch.

Meanwhile, to improve EUV throughput and cost, we have several projects. We are looking at new resists working with several materials vendors to improve printability and defectivity at lower dose. We are working on mask and design optimization to lower EUV dose. We have developed a carbon nanotube (CNT)-based pellicle that has much better transmission than the conventional polysilicon based pellicles.

AEI: What other significant R&Ds imec is doing at the moment that will have impact on the industry in the long term?

Samavedam: In the advanced patterning program, we explore ways to reduce EUV dose to improve throughput and cost without impacting line edge roughness and defectivity. We are also researching enabling the full eco-system for high NA EUV.

In addition, we continue to explore and benchmark various integration and module options for realizing CFET devices, which are likely to enable 4T standard cell designs. We also have extensive activities in enabling backside power delivery and functional backside.

In the backend, there is very good progress in incorporating airgaps in direct-etched high aspect-ratio metal lines to enable RC scaling. We have also demonstrated self-aligned vias with direct metal etched lines at 18nm pitch. We are researching graphene capping of metals to lower resistance and novel binary/ternary alloys to replace Cu and Ru eventually.