Keysight Technologies, Inc. introduces PCIe Designer, a new product in the Advanced Design System (ADS) product suite. Particularly, it supports simulation workflows based on industry standards for high-speed, high-frequency digital designs.

Moreover, PCIe Designer is an intelligent design environment for modeling and simulating the latest PCIe Gen5 and Gen6 systems. Keysight is also improving its electronic design automation (EDA) platform by adding new features to the existing Chiplet PHY Designer tool to estimate chiplet die-to-die link margin performance and Voltage Transfer Function (VTF) compliance measurement.

PCIe is a versatile and essential interface standard across a wide range of electronics industry segments. Specifically, due to its high-speed data transfer capabilities, scalability, and adaptability. Adoption spans from everyday consumer electronics to specialized applications in high-performance computing and critical infrastructure systems.

Complex PCIe designs support multi-link and multi-lane systems that involve a complex analysis setup between RootComplex and End-Point. Sometimes, incorporating mid-channel repeaters. Designers spend an inordinate amount of time preparing simulations that are prone to mistakes.

Moreover, simulations often lack vendor-specific algorithmic modeling interface (AMI) simulation models. These are requirements early in the design cycle for design space exploration. In addition, designers also need assurance that their prototype design will pass compliance testing before hardware fabrication.

Productivity, Workflow, and Compliance Improvement Features

The PCIe Designer automates the setup for multi-link, multi-lane, and multi-level (PAM4) PCIe systems using a smart design environment. Furthermore, it simplifies simulation setup and reduces time-to-first-insight.

The PCIe AMI modeler, which supports NRZ and PAM4 modulations, facilitates quick AMI model generation needed for PCIe system analysis. Furthermore, the AMI Model Builder gives designers a wizard-driven AMI model generation workflow to rapidly create models for both transmitters (Tx) and receivers (Rx).

Streamlined, simulation-driven virtual compliance testing enables designers to ensure design quality. The integrated, simulation-driven PCIe compliance test workflow reduces design costs by minimizing design iterations and shortening time-to-market.

Chiplet PHY Designer Enhancements

Chiplet PHY Designer is the EDA industry’s first simulation solution for Universal Chiplet Interconnect Express (UCIe) standards. Therefore, enabling predictions of die-to-die link margin, VTF for channel compliance analysis, and forwarded clock capability.

Chiplet PHY Designer includes new design exploration and report generation features that accelerate signal integrity analysis and compliance verification. Therefore, improving designer productivity and time-to-market.

Meanwhile, Hee-Soo Lee, Director of High-Speed Digital segment, Keysight EDA, said,“We continue to expand our standards-driven workflow approach to support our customers. Our high-speed digital product portfolio is leading the EDA industry with the most accurate and advanced simulation software for signal integrity analysis and compliance test validation.”

In addition, Lee said “Digital standards such as PCIe and UCIe are critical to the performance of electronic systems. Designers using our PCIe and UCIe simulation solutions in their workflows can shift left their development cycle to save significant time and cost.”

19 July 2024