Teradyne has introduced an integrated test cell solution designed to support the screening of semiconductor devices used in artificial intelligence (AI) and data center applications. Developed in collaboration with Tokyo Electron (TEL), the system aims to help manufacturers ensure device quality as chip architectures become increasingly complex.

The solution combines Teradyne’s UltraFLEXplus platform with TEL’s Prexa SDP (Singulated Device Prober) to deliver a production-ready approach to known good device (KGD) screening. It is designed for use by fabless semiconductor firms, foundries, and outsourced semiconductor assembly and test providers (OSATs).

Supporting Advanced Packaging and Chiplet Architectures

The announcement comes as AI and data center technologies continue to drive the adoption of chiplet-based designs. These architectures integrate multiple dies into advanced 2.5D and 3D packages, increasing both performance and manufacturing complexity.

In such configurations, a single faulty die can compromise the performance of an entire high-value package. The integrated test solution is designed to screen devices at multiple stages of the advanced packaging process, helping reduce this risk.

By enabling KGD screening earlier in the production cycle, the system aims to protect final yield, improve product quality, and maximize manufacturing output.

Designed for High-Volume Manufacturing

Teradyne and Tokyo Electron describe the joint solution as a validated test cell intended to reduce integration risks in high-volume manufacturing environments. The system coordinates testing and probing processes within a single integrated setup.

Within the test cell, Teradyne’s UltraFLEXplus instruments work in combination with TEL’s Prexa SDP technology. The prober maintains device temperature and manages the high-power dissipation characteristics typical of advanced AI silicon, enabling consistent and reliable testing performance.

This integration is designed to support the demanding requirements of next-generation semiconductor devices used in AI and data center applications.

Flexible, Open Ecosystem Architecture

The test solution is built on an open ecosystem architecture, allowing customers to configure the system according to their specific needs. It supports a range of complementary probe cards, manipulators, and interface technologies.

Manufacturers also have the flexibility to integrate the solution with other probers or testers, making it adaptable to a variety of production environments and workflows.

Addressing Rapid Innovation in AI Devices

As AI device development continues to accelerate, the need for reliable testing at every stage of production has become increasingly critical. The integrated test cell is intended to provide a dependable screening solution that keeps pace with rapid innovation in semiconductor design.

The collaboration between Teradyne and Tokyo Electron highlights the industry’s shift toward integrated, flexible testing platforms capable of addressing the challenges of advanced packaging and high-performance computing devices.

09 June 2026