IBM, Samsung Alliance Bares New Semiconductor Design

IBM and Samsung Electronics have announced a breakthrough in semiconductor design utilizing a new vertical transistor architecture that demonstrates a path to scaling beyond nanosheet. Furthermore, it has the potential to reduce energy usage by 85 percent compared to a scaled fin field-effect transistor (finFET)1.

This collaborative approach to innovation makes the Albany Nanotech Complex a world-leading ecosystem for semiconductor research and creates a strong innovation pipeline. Consequently, this would help address manufacturing demands and accelerate the growth of the global chip industry.

Delivers New Innovations

The new vertical transistor breakthrough could help the semiconductor industry continue its relentless journey to deliver significant improvements in many ways. This includes potential device architecture for semiconductor device scaling beyond nanosheet. In addition, it could also mean longer battery capacities for mobile phones and less carbon footprint for energy intensive processes.

IBM and Samsung collaboration has brought forward a breakthrough semiconductor design.

Furthermore, the development could also equate to continue expansion of Internet of Things (IoT) and edge devices with lower energy needs. This would mean operating in more diverse environments like ocean buoys, autonomous vehicles, and spacecraft.

“Today’s technology announcement is about challenging convention and rethinking how we continue to advance society and deliver new innovations that improve life, business and reduce our environmental impact,” Dr. Mukesh Khare, Vice President, Hybrid Cloud and Systems, IBM Research. “…IBM and Samsung are demonstrating our commitment to joint innovation in semiconductor design and a shared pursuit of what we call ‘hard tech.'”

Brings New Dimension to Moore’s Law

Historically, transistors have been built to lie flat upon the surface of a semiconductor, with the electric current flowing laterally, or side-to-side, through them. With new Vertical Transport Field Effect Transistors (VTFET), IBM and Samsung have implemented transistors built perpendicular to the surface of the chip with a vertical, or up-and-down, current flow.

The VTFET process addresses many barriers to performance and limitations to extend Moore’s Law as chip designers attempt to pack more transistors into a fixed space. It also influences the contact points for the transistors, allowing for greater current flow with less wasted energy. Overall, the new design aims to deliver a two times improvement in performance or an 85 percent reduction in energy use as compared to scaled finFET alternatives1.

Recently, IBM announced the 2nm chip technology breakthrough that will allow a chip to fit up to 50 billion transistors in a space the size of a fingernail. VTFET innovation focuses on a whole new dimension, which offers a pathway to the continuation of Moore’s Law. 

Long List of IC Breakthroughs

Moreover, the companies also announced that Samsung will manufacture IBM’s chips at the 5nm node. These chips will make its way to IBM’s own server platforms. This follows the announcement in 2018 that Samsung would manufacture IBM’s 7nm chips, which became available in the IBM Power10 servers earlier this year. The IBM Telum processor, also revealed earlier this year, will also have Samsung as manufacturer using IBM’s designs.

IBM’s legacy of semiconductor breakthroughs also includes the first implementation of 7nm and 5nm process technologies and High-k metal gate technology. Also part of them are channel SiGe transistors, single cell DRAM, the Dennard Scaling Laws, and chemically amplified photoresists. Furthermore, copper interconnect wiring, Silicon on Insulator technology, multi core microprocessors, embedded DRAM, and 3D chip stacking are also part of the legacy.

1 VTFET nanosheet and scaled FinFET device simulation results are compared at the same footprint and at an aggressive sub-45nm gate pitch. VTFET nanosheets provides ~ 2X performance of the scaled FinFET at equivalent power due to VTFET maintaining good electrostatics and parasitics while FinFET performance is impacted by severe scaling constraints. Or VTFET could provide as much as 85% power reduction compared to the scaled FinFET architecture as compared at an equivalent frequency on the extrapolated power-performance curves.